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[Other resource] fifo程序

Description: 用verilog语言在fpga中实现fifo功能！-using Verilog language in which they simply realize fifo function!
Platform: | Size: 973 | Author: 刘涛 | Hits:

[Other resource] fifo

Description: 使用Verilog语言编写，把FPGA配置成一个fifo
Platform: | Size: 19659 | Author: achesser | Hits:

[Other resource] fifo-1117

Description: 这是异步FIFO的VHDL实现代码，已经在FPGA上通过实践证明，运行状态良好
Platform: | Size: 20434 | Author: 杨宇 | Hits:

[Documents] 异步FIFO结构及FPGA设计

Description: 介绍异步FIFO的概念、应用及其结构，分析实现异步FIFO的难点问题及其解决办法；在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现。
Platform: | Size: 169984 | Author: sht816dzkd@163.com | Hits:

[Driver Develop] fifo的FPGA实现

Description: fifo的FPGA实现
Platform: | Size: 3920 | Author: yongyu528@163.com | Hits:

[VHDL-FPGA-Verilog] EPP

Description: 并口的EPP协议，与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
Platform: | Size: 1024 | Author: 陈刚 | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Software Engineering] fifo_generator_ug175

Description: 该文档是有关利用XINLIX的FPGA如何实现FIFO的生成及如何应用的文章。-The document is related to the FPGA using XINLIX how to achieve FIFO generation and how to use the article.
Platform: | Size: 714752 | Author: cobain | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations.
Platform: | Size: 378880 | Author: lsg | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[USB develop] cmos_fifo_usb

Description: cmos数据到fifo再到usb的fifo部分程序(68013a)-cmos data to fifo the fifo to the usb part of the procedures (68013a)
Platform: | Size: 158720 | Author: | Hits:

[VHDL-FPGA-Verilog] sopc_avalon_audio_dac_fifo

Description: fpga嵌入式系统组件，可以很方便的扩展，是个实例的例子，可以实现歌曲播放-FPGA embedded system components, it is easy to expand, is an example of the example, you can realize music player
Platform: | Size: 14336 | Author: dahai | Hits:

[VHDL-FPGA-Verilog] sp6ex19

Description: FPGA片内FIFO实例，对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
Platform: | Size: 5181440 | Author: 没伞的孩子 | Hits:

[Other] FIFO

Description: STM32通过与FPGA通信读取FPGA的串行FIFO(STM32 and FPGA FIFO communication)
Platform: | Size: 9152512 | Author: k77 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: fifo的使用，在Altera的开发工具(fifo use in Altera's development tools)
Platform: | Size: 21504 | Author: 红色叶子 | Hits:

[VHDL-FPGA-Verilog] fifo_FPGA

Description: 68013 FIFO 接口程序，USB开发、VHDL开发(68013 FIFO USB VHDL FPGA)
Platform: | Size: 887808 | Author: 郑韬 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: IL SAGIT D'UN FIFO EN DESCRIPTION DE LANGUAGE vhdl
Platform: | Size: 1024 | Author: alaala | Hits:

[VHDL-FPGA-Verilog] Router fifo for NOC

Description: Router 8-bit fifo design, written in Verilog
Platform: | Size: 822 | Author: spgp1306 | Hits:

[Communication-Mobile] fifo

Description: First In First Out for fpga
Platform: | Size: 28672 | Author: kesi | Hits:

[VHDL-FPGA-Verilog] 通信协议FPGA

Description: 本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.)
Platform: | Size: 19605504 | Author: 蔺娇娇 | Hits:
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